The pipelined ADC is a popular ADC system architecture used in a wide variety of applications including for example, digital imaging, data transmission, and wireless communications. In general, an analog input signal is sampled and held while a first stage quantizes the sample into digital bits. The digitized sample is then fed into a digital-to-analog converter, hereinafter DAC, and the resulting analog output is subtracted from the original sample. The residue thus obtained is then typically gained up by a desired gain factor and passed to a next similar stage. The process is repeated as the sample continues through additional stages of the pipeline. Since the bits from each stage are determined at different times, all of the bits corresponding to a given sample are corrected for time-alignment, typically using shift registers, prior to being output.
Quantization error inevitably results from the conversion of the input signal sample. An ideal ADC output may be described in terms of the formula: y=xin+εQ [Equation 1], where xin is the input signal, and εQ is the inherent conversion uncertainty, or quantization error. Various problems arise in the implementation of pipelined ADCs, however, causing departure from the ideal. Additional errors are caused in large part by nonlinearities introduced by circuit component mismatch. In switched-capacitor ADC implementations, for example, inherent capacitor mismatch in the DAC is a major source of error. In switched-current implementations, resistor mismatch is a major error source. In general, for high accuracy in pipelined ADCs, some form of error correction is required.
Forms of error correction known in the arts include element trimming. One-time element trimming is simply the testing and adjustment of the ADC system to compensate for component mismatch. A major shortcoming of element trimming, as with any one-time error correction technique, is that it is unable to respond to the drift of component values over time, which may cause accuracy to deteriorate. Other disadvantages include the increased test time and additional circuitry required. Other forms of error correction familiar in the arts include element randomization, element shaping, and various techniques for analog and digital calibration. Numerous difficulties remain with such techniques, however, including but not limited to the requirement for additional ADC elements, reduced conversion rates, and inability of non-continuous calibration to adjust for changing conditions.
To address these and other problems, there is a need for improved systems and methods for continuous digital background calibration in pipelined ADC architectures.